1. Field of the Invention
The invention relates to the field of generation of clock signals with a delay line, particularly for metal-oxide-semiconductor (MOS) circuits.
2. Prior Art
In integrated circuit memories, processors, as well as other circuits, it is necessary to have clock or timing signals. For instance, in dynamic, random-access memories, many clock signals are required for each memory cycle to latch addresses, decode the addresses, access the array, precharge nodes, control refreshing, etc. Obviously, by generating these signals "on-chip" the need for precision clock generators, external to the integrated circuit is eliminated.
Generally in the prior art, an externally applied pulse is delayed on-chip to provide timing signals. This delay is provided using the charge-discharge characteristics of a resistor-capacitor network or of an MOS transistor-capacitor network in the case of MOS circuits. The length of the delay is controlled in these cases by the amount of resistance, capacitance or by the characteristics of an MOS transistor.
This prior art technique for generating on-chip timing signals does not result in accurate signals, in terms of time. The large variations, for example, in MOS circuit characteristics due to typical wafer processing, supply voltage variations and operating temperature cause substantial variations in timing delays. In a typical MOS circuit, variations from 2:1 to as high as 8:1 are encountered.
As will be seen, the present invention provides a circuit for generating clock signals which have a very high timing accuracy and insensitivity to variations from wafer processing, supply voltage and temperature. In addition, the timing accuracy with the present invention has the unusual characteristic of improving with increased value of the desired delay.